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CS51411, CS51412, CS51413, CS51414
Some representative efficiency data is shown in Figure 10.
100
80
60
40
Vin = 5.5 V, Vout= 3.3 V
20
Vin = 7.5 V, Vout = 5.0 V
Vin = 15V, Vout = 12 V
0
0
500 1000
I OUT , OUTPUT CURRENT (mA)
1500
Figure 11. A CS51411 Buck Regulator is Synced by an
External 350 kHz Pulse Signal
Figure 10. Efficiency versus Output Current
More detailed information is available in the ON
Semiconductor application note AND8276/D on V2 and the
CS5141x demonstration board number.
Error Amplifier
The CS5141X has a transconductance error amplifier,
whose noninverting input is connected to an Internal
Reference Voltage generated from the on ? chip regulator. The
inverting input connects to the V FB pin. The output of the
error amplifier is made available at the V C pin. A typical
frequency compensation requires only a 0.1 m F capacitor
connected between the V C pin and ground, as shown in
Figure 1. This capacitor and error amplifier’s output
resistance (approximately 8.0 M W ) create a low frequency
pole to limit the bandwidth. Since V2 control does not require
a high bandwidth error amplifier, the frequency
compensation is greatly simplified.
The V C pin is clamped below Output High Voltage. This
allows the regulator to recover quickly from overcurrent or
short circuit conditions.
Oscillator and Sync Feature (CS51411 and CS51413 only)
The on ? chip oscillator is trimmed at the factory and requires
no external components for frequency control. The high
switching frequency allows smaller external components to be
used, resulting in a board area and cost savings. The tight
frequency tolerance simplifies magnetic components election.
The switching frequency is reduced to 25% of the nominal
value when the V FB pin voltage is below Frequency Foldback
Threshold. In short circuit or overload conditions, this reduces
the power dissipation of the IC and external components.
An external clock signal can sync CS51411/CS51414 to a
higher frequency. The rising edge of the sync pulse turns on the
power switch to start a new switching cycle, as shown in
Figure 11. There is approximately 0.5 m s delay between the
rising edge of the sync pulse and rising edge of the V SW pin
voltage. The sync threshold is TTL logic compatible, and duty
cycle of the sync pulses can vary from 10% to 90%. The
frequency foldback feature is disabled during the sync mode.
Power Switch and Current Limit
The collector of the built ? in NPN power switch is
connected to the V IN pin, and the emitter to the V SW pin.
When the switch turns on, the V SW voltage is equal to the
V IN minus switch Saturation Voltage. In the buck regulator,
the V SW voltage swings to one diode drop below ground
when the power switch turns off, and the inductor current is
commutated to the catch diode. Due to the presence of high
pulsed current, the traces connecting the V SW pin, inductor
and diode should be kept as short as possible to minimize the
noise and radiation. For the same reason, the input capacitor
should be placed close to the V IN pin and the anode of the
diode.
The saturation voltage of the power switch is dependent
on the switching current, as shown in Figure 12.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0 0.5 1.0 1.5
SWITCHING CURRENT (A)
Figure 12. The Saturation Voltage of the Power Switch
Increases with the Conducting Current
Members of the CS5141X family contain pulse ? by ? pulse
current limiting to protect the power switch and external
components. When the peak of the switching current reaches
the Current Limit, the power switch turns off after the
Current Limit Delay. The switch will not turn on until the
next switching cycle. The current limit threshold is
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